1 demo manual dc393 ltc1564 filter board dc393f evaluation board for ltc1564 digitally controlled antialiasing filter and 4-bit p.g.a. , ltc and lt are registered trademarks of linear technology corporation. descriptio u this demonstration circuit allows the user to evaluate the ltc ? 1564 digitally controlled antialiasing filter. the cutoff frequency (f c ) and passband gain are fully programmable while the shape of the lowpass response is fixed. a latching digital interface stores f c and gain settings or it can be bypassed for control directly from the pins through either the on-board toggle switches or using the optional connector to control the pins externally. the ltc1564 operates from 2.7v to 10v total supply voltage (single or split supplies) and comes in a 16 pin surface mount ssop. this board demonstrates proper layout, bypassing and optional buffering to achieve best performance. applica- tions include dsp antialiasing and reconstruction filtering, communications and instruments with high dynamic range, up to 20 bits, and sampling rates to 300+ kilosamples per second. frequency response demo circuit some key features of this demo circuit include: ? 4-bit digitally controlled 8th order lowpass filter ?f c = 10khz to 150khz in 10khz steps ? 4-bit digitally controlled programmable gain amplifier ? g = 1 to 16 in 1v/v steps ? 100db attenuation at 2.5 ? f c ? rail-to-rail input and output range ? miniature 16-pin ssop package f in /f c 0.1 gain (db) 40 20 0 ?0 ?0 ?0 ?0 100 120 140 110 393a ta01 a: f c = 10khz, gain = 1, v in = 1v rms b: f c = 10khz, gain = 16, v in = 62.5mv rms c: f c = 150khz, gain = 1, v in = 1v rms d: f c = 150khz, gain = 16, v in = 62.5mv rms a c b d typical perfor a ce characteristics a d board photo u uw
2 demo manual dc393 ltc1564 filter board dc393f j1 1 5 3 7 11 9 13 17 15 19 23 21 1 5 3 7 11 9 13 17 15 19 23 21 2 6 4 8 12 10 14 18 16 20 24 22 2 6 4 8 12 10 14 18 16 20 24 22 393 schem1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out v en cs/hold f3 f2 f1 f0 in agnd v + rst g3 g2 g1 g0 r21 220 rst r22 220 r23 220 r24 220 r25 220 r15 220 r16 220 r17 220 r18 220 r19 220 r20 220 12 sw1 1 3 10 11 2 9 4 6 7 up logic 0 8 5 0 1 0 1 up rst cs 65 4 123 c5 0.1 f c6 1 f c11 opt r14 opt c4 0.1 f c3 opt c1 0.1 f opt c12 opt 7 4 c9 opt 3528 c7 10 f 16v 2 jp3 1 3 j4 in in 5 4 3 2 r26 opt in 1 r8 10k r13 10k r9 10k r10 10k r11 10k g3 g2 g1 g0 g3 g2 g1 g0 j3 out out out opout agnd 5432 1 sgnd agnd sgnd v v opv opv + logic 1 logic 0 logic 0 logic 0 return single supply dual supply 2 jp2 3 1 v v 2 jp1 3 enable 1 logic 0 c8 10 f 16v jp4 2 1 v + v + agnd 12 sw2 1 3 10 11 2 9 4 6 7 up logic 0 notes: unless otherwise specified 1. all resistors are in ohms, 0805; all capacitors are in microfarads, 0805 2. switches are shown with rocker in ?p?position, giving a logic 1 state 8 5 0 1 logic 0 logic 1 r4 10k j2 opout opt opout 5432 1 r5 10k r6 10k r7 10k f0 f1 f2 f3 f3 f2 f1 f0 logic 1 logic 1 v + logic 0 sw3 en cs logic 1 ltc1564cg u2 logic 1 r12 10k rst logic 1 r27 10k r3 0 + c2 0.1 f opt c10 opt 3528 + + opv opv + u1 tbd 3 2 sgnd sgnd r1 opt r2 opt ltc1564 1 2 3 4 5 6 7 8 top view g package 16-lead plastic ssop 16 15 14 13 12 11 10 9 out v en cs/hold f3 f2 f1 f0 in agnd v + rst g3 g2 g1 g0 package a d sche atic diagra wu w
3 demo manual dc393 ltc1564 filter board dc393f parts list reference quantity part number description vendor telephone (2) agnd, (3) sgnd, 25 2501-2 1-pin terminal turret, 0.094" mill-max (516) 922-6000 f0Cf3, g0Cg3, in, out, cs, rst, en, v + , v C , logic 0, logic 1, opv + , opv C , opout c1Cc3, c9Cc12 optional tbd capacitor tbd c4, c5 2 0805zc104mat1a 0.1 m f 10v x7r capacitor avx (843) 946-0362 c6 1 0805zc105mat1a 1 m f 10v x7r capacitor avx (843) 946-0362 c7, c8 2 emk325bj106mn 10 m f 16v, 20% 1210 xr5 capacitor taiyo yuden (408) 573-4150 j1 optional tbd header tbd j2 optional tbd bnc tbd j3, j4 2 112404 bnc connex (805) 378-6464 jp1, jp2, jp3 3 3801s-3g2 header, 3 pins 1 row 0.1"cc comm con (626) 301-4200 jp4 1 3801s-2g2 header, 2 pins 1 row 0.1"cc comm con (626) 301-4200 jp1Cjp4 4 ccij230-g shunts for jp1Cjp4 , 0.1"cc comm con (626) 301-4200 r1, r2, r14, r26 optional tbd resistor tbd r3 1 cj10-000m 0 w 1/16w 5% resistor aac (800) 508-1521 r4Cr13, r27 11 cr10-103jm 10k 1/16w 5% resistor aac (800) 508-1521 r15Cr25 11 cr10-221jm 220 w 1/16w 5% resistor aac (714) 255-9186 sw1, sw2 2 76stc04 switch spdt-4 form c gray hill (708) 354-1040 sw3 1 76stc02 switch spdt-2 form c gray hill (708) 354-1040 u1 optional tbd ic tbd u2 1 ltc1564cgn ic ltc (408) 432-1900 demo board operation and connection hints when using the dc393 demo board, the following steps should be taken to ensure proper operation for evaluating the ltc1564. this demo board was designed for either single or dual supply operation. the ltc1564 has only three analog pins: input, output and a half-supply reference voltage point, agnd. the other pins are digital controls and power supply. step 1: check the jp1 jumper setting. this jumper is the digital chip enable input for the ltc1564. install the jumper between pins 1 and 2 for normal operation (en = 0) or between pins 2 and 3 (en = 1) for shutdown mode with reduced supply current. the active circuitry in the ltc1564 shuts off and its output assumes a high operatio u impedance state. if f and g bits are latched (cs/hold = 1) during the shutdown state, the latch will retain its contents. step 2: check the jp2 jumper setting. the ltc1564s cmos-level inputs accept cmos logic levels, either rail- to-rail or, alternatively, 0v and 5v when the part is oper- ated from 5v supplies. jumper jp2 sets the logic 0 level to either sgnd or v C . install the jumper between pins 1 and 2 for logic 0 = v C or between pins 2 and 3 for logic 0 = sgnd. step 3: check the jp3 jumper setting. used for selecting single or dual power supply operation. install the jumper between pins 1 and 2 for dual supply or between pins 2 and 3 for single supply.
4 demo manual dc393 ltc1564 filter board dc393f operatio u logic 1, the f pins cease to have effect and the latch holds the previous values. the f code control is the filters cutoff frequency f c in 10khz steps up to 150khz, as summarized in table 2. thus f c is proportional to the binary value of the f code. the frequency setting (f) and gain setting (g) are each four-bit codes entered through the f and g digital input pins (table 3). also, setting the f code to 0000 engages a mute state where the filter remains fully powered but the input pin is disconnected inside the ltc1564 and output noise becomes even lower than in normal filter operation. step 7: check the sw3 switch positions. the cs/hold switch is the digital enable input for the internal latch holding f and g bits. logic 0 makes the latch transparent so that the f and g switches directly control the filters cutoff frequency and gain. logic 1 holds the last values of these switches prior to the transition. the rst switch is the digital asynchronous reset input for the internal f and g latches. logic 0 at any time will reset these latches to zero. table 1. programming the ltc1564 gain nominal maximum input signal level nominal g3 g2 g1 go passband gain (v p-p ) input impedance (at output of internal latch) (v/v) (db) dual 5v single 5v single 3v (k) 0000 10 1053 10 0 0 0 1 2 6 5 2.5 1.5 5 0 0 1 0 3 9.5 3.33 1.67 1 3.33 0 0 1 1 4 12 2.5 1.25 0.75 2.5 0100 514 210.6 2 0 1 0 1 6 15.6 1.67 0.83 0.5 1.67 0 1 1 0 7 16.9 1.43 0.71 0.43 1.43 0 1 1 1 8 18.1 1.25 0.63 0.38 1.25 1 0 0 0 9 19.1 1.1 0.56 0.33 1.11 1 0 0 1 10 20 1 0.5 0.3 1 1 0 1 0 11 20.8 0.91 0.45 0.27 0.91 1 0 1 1 12 21.6 0.83 0.42 0.25 0.83 1 1 0 0 13 22.3 0.77 0.38 0.23 0.77 1 1 0 1 14 22.9 0.71 0.36 0.21 0.71 1 1 1 0 15 23.5 0.67 0.33 0.2 0.66 1 1 1 1 16 24.1 0.63 0.31 0.19 0.63 step 4: check the jp4 jumper setting. this jumper when installed connects the 10k pull-up resistors to v + for all digital inputs of the ltc1564. step 5: check the sw1 switch positions. the four switches labeled g3, g2, g1, g0 create a 4-bit binary word for the ltc1564s digital gain control (g code) inputs. g3 is the most significant bit (msb). these switches program the ltc1564s passband gain through the inter- nal latch, which passes the bits directly when the cs/hold input is at logic 0. when cs/hold changes to logic 1, the g switches cease to have effect and the latch retains the previous input values. this gain control is linear in ampli- tude: nominal passband gain of the ltc1564 is the binary value of the g code plus one, as shown in table 1. step 6: check the sw2 switch positions. the four switches labeled f3, f2, f1, f0 create a 4-bit binary word for the ltc1564s digital frequency control (f code) inputs. f3 is the most significant bit (msb). these switches program the ltc1564s cutoff frequency f c through the internal latch, which passes the bits directly when the cs/hold input is at logic 0. when cs/hold changes to
5 demo manual dc393 ltc1564 filter board dc393f operatio u step 8: connecting power supply lines. electrically clean supplies and a low impedance ground are important for the high dynamic range and high stopband suppres- sion available from the ltc1564. low noise linear power supplies are recommended. switching supplies can be used with sufficient filtering to prevent switching noise coupling into the signal path, reducing dynamic range. step 9: input connection. connect the input signal to the in bnc connector. the input of the ltc1564 is connected directly to the in bnc with an optional r26 shunt resistor connected to sgnd. table 1 shows how the maximum input signal level is inversely proportional to the gain of the filter for different supplies. step 10: output connection. connect your monitoring device (oscilloscope, network analyzer, etc.) to the out bnc connector. the output of the ltc1564 is designed to drive nominal load of 5k w and 50pf. change the series resistor r3 from 0 w to 500 w for capacitances greater than 50pf. consult the ltc1564 data sheet for more details on output loading issues. table 2. programming the ltc1564 cutoff frequency f3 f2 f1 fo nominal f c (at output of internal latch) (cutoff frequency) 0 0 0 0 0 (mute state) 0 0 0 1 10khz 0 0 1 0 20khz 0 0 1 1 30khz 0 1 0 0 40khz 0 1 0 1 50khz 0 1 1 0 60khz 0 1 1 1 70khz 1 0 0 0 80khz 1 0 0 1 90khz 1 0 1 0 100khz 1 0 1 1 110khz 1 1 0 0 120khz 1 1 0 1 130khz 1 1 1 0 140khz 1 1 1 1 150khz table 3. ltc1564 digital controls and modes en rst cs/hold f 3 f 2 f l f o g 3 g 2 g 1 g 0 function 1 1 1 xxxxxxxxs hutdown mode. filter disabled. latch holds f and g inputs present when last cs/hold = 0 1 1 0 xxxxxxxxs hutdown mode. filter disabled. latch accepts f and g inputs 1 0 x xxxxxxxxs hutdown mode. filter disabled. latch contents (f and g) reset to all zeros 0 1 0 0 0 0 0 x x x x mute mode. reduced noise 0 0 x xxxxxxxxm ute mode. reduced noise latch contents (f and g) reset to all zeros 0 1 1 other than 0 0 0 0 x x x x normal filtering operation. latch holds f and g inputs present when last cs/hold = 0 0 1 0 other than 0 0 0 0 x x x x normal filtering operation. filter responds directly to f and g input pins x = dont care
6 demo manual dc393 ltc1564 filter board dc393f top solder mask top solder paste top silkscreen pcb layout a d fil uw
7 demo manual dc393 ltc1564 filter board dc393f pcb layout a d fil uw top layer bottom layer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8 demo manual dc393 ltc1564 filter board dc393f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2002 lt/tp 0902 500 ? printed in usa pcb layout a d fil uw bottom silkscreen pc fab drawi g u bottom solder mask 0.017 notes: unless otherwise specified 1. material: fr4 or equivalent epoxy, 2 oz copper clad thickness 0.062 0.006 total of 2 layers 2. finish: all plated holes 0.001 min/0.015 max copper plate electrodeposited tin-lead composition before reflow, solder mask over bare copper (smobc) 3. solder mask: both sides using lpi or equivalent 4. silkscreen: using white nonconductive epoxy ink 5. unused smd components should be free of solder 6. fill up all vias with solder 7. scoring hole chart number symbol diameter of holes plated a 0.125 4 yes b 0.094 26 yes c 0.070 2 no d 0.055 15 yes e 0.050 4 yes f 0.035 65 yes g 0.020 36 yes total holes 152 g g g g g g g g g g g g g g g g g g g g g c c f f f f f f f f f f f f d d d d d d d d d d d d d d d b b b b b b b b b b b b b b b b b b b b b b b b b b a a a a e e e e 2.80in 2.95in 393a fab dwg
linear technology corporation ltc1564cg bill of materials DC393A qty-225 11/8/2004 11:17 am item qty referenc e part description manufacture / part # 1 26 2 agnd, 4 sgnd,f0-f3,g0-g3,en,in,out,opout testpoint, turret, .094" mill-max 2501-2 logic0,logic1,rst,cs,opv+,opv-,v+,v- 2 0 c1-c3,c9-c1 2 cap., 0805 opt 3 2 c4,c5 cap., x7r 0.1uf 10v avx, 0805zc104mat1a 4 1 c6 cap., x7r 1uf 10v avx, 0805zc105mat1a 5 2 c7,c8 cap, x5r, 10uf 16v, 20%, 1210 taiyo yuden emk325bj106mn 6 3 jp1,jp2,jp3 header, 3 pins, 1 row, .1"cc comm con 3801s-3g2 7 1 jp4 header, 2 pins, 1 row, .1"cc comm con 3801s-2g2 8 4 shunts for jp1-jp4 shunt, .100 comm con ccij230-g 9 0 j1 header, 24 pins, 2 row, .1"cc opt 10 0 j2 conn, bnc, 5 pins opt 11 2 j3,j4 conn, bnc, 5 pins connex 112404 12 0 r1,r2,r14,r2 6 res, 0805 opt 13 1 r3 res., chip 0 1/16w 5% aac, cj10-000m 14 11 r4-r13,r27 res., chip 10k 1/16w 5% aac, cr10-103jm 15 11 r15-r25 res., chip 220 1/16w 5% aac, cr10-221jm 16 2 sw1,sw2 switch,spdt-4,form c grayhill, 76stc04 17 1 sw3 switch,spdt-2,form c grayhill, 76stc02 18 0 u1 ic, so8 opt 19 1 u2 ic, ltc1564cgn, ssop16g linear tech., ltc1564cgn page 1 - of - 1
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